Beyond Moore's Law: the next golden age of computer architecture
The ‘Information Age,’ is signified by ceaseless advancements over the last five decades. Computing technologies are no stranger to advancement – what used to be a roomful of computers now fits into the palm of your hands in the form of always-on-internet-connected smart devices. Or snack-like microchips to nanotechnology.
The sole constant during this evolution has been the modest creator of all these advancements: the Moore's Law (the number of transistors on a microchip roughly doubles over every two years). Recalling Gordon Moore’s own words, “No exponential is forever, but ‘forever’ can be delayed!” – we might be at a point where we bid adieu to Moore’s Law.
In spite of exponential progress, a transistor continues to remain a physical device and engineers are struggling to further shrink it which is impacting the prophecy. Not to mention the financial strain; a 3nm chip design costs millions more to design than a 5nm chip.
In trying to mitigate the fading of Moore’s Law, Turing laureates Dr. John L. Hennessy and Dr. David A. Patterson have said, “High-level, domain-specific languages and architectures, freeing architects from the chains of proprietary instruction sets, along with demand from the public for improved security, will usher in the next golden age of computer architecture.”
The next 50 years of computing could be characterized by the above alongside improved software frameworks, next-generation compilers, alternatives to silicon semiconductors and open-collaborative ecosystems. Visionaries discuss this and more at Thoughtworks e4r: Engineering For Research™ Symposium 2022.
Professor of Electrical Engineering - IIT Bombay, India
Souvik Mahapatra's research interests are in the area of CMOS logic and flash memory devices, with special focus on device scaling and reliability. He has published more than 150 papers in peer reviewed journals and conferences, delivered invited talks in major IEEE conferences including the International Electron Devices Meeting (IEDM), delivered tutorials in IEEE International Reliability Physics Symposium (IRPS), and served as a reviewer and committee member for many IEEE journals and conferences. He has close research collaborations with many industries in the semiconductor integrated circuits technology area. He is active within the IEEE IRPS community.
Professor and Director of Digital Science Centre, University of Virginia
Dr Fox is a distinguished Professor and Director of Digital Science Centre, which aims to make supercomputing tools more accessible for researchers striving to make progress on a wide range of global challenges, including health care, particle physics and defense. He is renowned for his work in high-performance computing - processing large, complex sets of data at very high speeds, and parallel computing. He has used those methods to examine everything from quarks to earthquakes to ice sheets. A fellow of both the American Physical Society and the Association for Computing Machinery, he has received numerous awards for his research, teaching and diversity outreach efforts.
Co-Founder, CEO - Morphing Machines, India
Dr. Narayan and team is building a multi-core processor to enable businesses to build energy efficient, high performance systems. Her innovation focuses on REDEFINE™ - a processor indigenously conceived, developed, and implemented in India, that is an excellent replacement and upgrade for CPUs and GPUs from multinational brands.
Professor - ETH Zurich
Dr. Mutlu is one of the best minds in the Data Intensive Computing arena. He was named an ACM Fellow for "contributions to computer architecture research, especially in memory systems" and an IEEE Fellow for "contributions to computer architecture research and practice." In 2018, he was elected as a member of the Academy of Europe (Academia Europaea) due to his “outstanding achievements as a researcher."
Professor - Indian Institute of Science
Dr. Selvaraj’s area of research includes high-speed integrated photonic devices, development of photonic materials, and device platform for on-chip photonic sensors. He has been actively involved for over a decade in the area of silicon photonics to develop state-of-the-art process and device technology for CMOS compatible photonic integrated circuit for high-speed optical interconnects.
Associate Professor, Technion - Israel Institute of Technology
Dr. Silberstein heads the team at Accelerated Computing Systems Lab that uses bleeding-edge hardware to build new easy-to-program high performance systems with strong security. Their projects include new operating systems for GPUs, FPGAs and SmartNICs, data-center scale OS for disaggregated architectures, new defenses against hardware side channels and speculative execution attacks, new compilers and runtimes for secure processors, distributed programs on programmable switches and accelerated machine learning.
Professor - Technische Universität Dresden
Prof. Castrillon is a founding member of the executive committee of the ACM “Future of Computing Academy”. He is a young scientist working on cutting-edge compilers beneficial for heterogeneous architectures. Currently, he is the Chair for Compiler Construction at Technical University at Dresden.
Professor, University of Illinois
Founder, CEO - Charmworks
ACM and IEEE Fellow Dr. Kale is perhaps best known for Charm++, a parallel object-oriented framework based on C++ for supercomputing applications. He is a leading researcher working in the area of parallel and distributed computing for over 30 years.
General Manager, CHIPS Alliance - Linux Foundation
Rob Mains is a 40 year industry veteran with in depth experience in software development, electronic design automation, IT management, semiconductor technology, microprocessor circuit design, and chip construction methodology. He is a former engineering vice president of Oracle and Sun Microsystems distinguished engineer, where he led an organization of over 200 software researchers and developers. He is the holder of 13 U.S. patents.
Senior Fellow - AMD
Raja Swaminathan is responsible for package architecture and advanced technology strategy and development at AMD. He was a package architect at Intel for 13 years, moved to Apple to architect their new silicon package architectures before moving to AMD to drive their industry leading chiplet architecture integration. He received his Bachelors’ from IIT Madras in 2000, PhD from Carnegie Mellon in 2005. He has over 35 US patents in the field and he is an IEEE Senior Member.
Co-Managing Director, India - Thoughtworks
Sudhir is passionate about delivering the best technology solutions to the world. His background lies in product management, and was part of the founding team of Thoughtworks product division. Since becoming Managing Director for Thoughtworks India, Sudhir has overseen the phenomenal growth in the region in recent years. He also heads Thoughtworks Data & AI service, helping regional teams develop specialist services for our clients.
Global Head of Technology - Thoughtworks
Dave is deeply immersed in technology and it's impact on business and society- through software architecture, analytics, infrastructure, emergent ideas, prototyping and large scale program management. He is a Fellow of the Chartered Management Institute. He advises board C-suites and executive committees on lean enterprise and technical strategic thinking. Dave also sits on technology advisory groups for Government, independent companies, funded startups and standards bodies.
Computer Scientist, Engineering for Research - Thoughtworks
Harshal has worked on complex computational problems such as modeling and simulation of human behaviour, disaster response simulation, and development of model-driven control systems for large scientific apparatus. His research interests include complex systems, human-centric systems, modeling & simulation of social dynamics, domain-specific languages & compiler construction, software engineering, data visualization, knowledge representation, control systems, and distributed computing. Harshal is the organizer of the e4r™ Symposium.