Posit Enhanced Rocket Chip (PERC) is a project that aims to provide support for posit arithmetic using the free and open RISC V ISA. Posit arithmetic is a hardware friendly, dynamic floating point representation that ensures better accuracy and precision using a system that minimizes the number of unusable representations and introduces a higher dynamic range which can serve as a substitute for the IEEE-754 2008 floating point standard.
We started by implementing a library of parameterized posit hardware units using Chisel HDL which have been tested using a standard test generator. These hardware units are then integrated to form the Posit Processing Unit / Posit FPU and added to the core pipeline of the Rocket core (present inside the Rocket Chip SoC generator) which replaces the inhouse IEEE 754 FPU.
ISA support for posit arithmetic has been achieved by utilizing the F and D standard ISA extensions provided by RISC V for single precision and double precision IEEE 754 floating point arithmetic. This approach ensures minimal modification to the RISC V software tool chain to meaningfully use such an architecture.
The Rocket chip circuit instances with the PPU added were also integration tested using a modified version of the RISC V ISA test suite for posit arithmetic.
A lot more can be done in this space and we continue to explore newer ways to adopt posit arithmetic into modern computer architectures.